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Design and Optimization of Stacked Nanosheet FET and FinHBT for Ultra-Scaled SoC


Combining digital computation, analog, and radio frequency (RF) circuitry, a highly functional systems-on-chip (SoC) design is a favorable choice for various applications like mobile systems, embedded systems, and space applications. While the aggressive scaling continues for digital applications, the analog/RF performance of these highly scaled devices is lagging. To achieve an SoC technology with advanced ultra-scaled digital transistors and compatible RF/Mixed-Mode devices, this work is divided into two major sections. In the first section, TCAD simulation of Stacked Nanosheet FETs (NSFETs) based on quantum physics has been performed. The study focuses on critical device parameters including LG, TNS, parasitic resistance, and EOT. The TDDB behavior of NSFETs with different corner rounding radii is studied closely with a discrete trap based TCAD simulation. In the second section, an innovative lateral SiGe FinHBT is proposed to leverage the lateral scaling capability of the FinFET CMOS fabrication platform to establish high-speed BiCMOS VLSI SoCs for THz/mixed-mode applications. A complete CMOS compatible process flow of fabricating a nanoscale lateral SiGe FinHBT on an SOI wafer has been developed. A prototype of the lateral SiGe FinHBT has been fabricated and characterized. Based on the results, it is projected that the lateral SiGe FinHBT can potentially reach fT/fMAX > 750 GHz with further process optimization and scaling.

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