UC Santa Cruz

To efficiently exploit the growing heterogeneity in systems, we need to know their software-hardware agreement for instruction reordering. Without the knowledge of these underlying contracts and how shared memory behaves on heterogeneous systems, concurrent code cannot be written safely, as unexpected reorderings by the hardware can cause data races that might not exist in an architecture with a sequentially consistent memory model. These agreements become especially complex in heterogeneous platforms because different systems can allow different reorderings, making it crucial to understand the behavior of shared memory. This work aims to explore the memory consistency model (MCM) of integrated CPU-GPU systems. We propose a compiler to generate memory consistency tests for empirically testing the MCM of these heterogeneous systems. We show that all four memory reorderings can be observed on the NVIDIA Jetson Orin Nano. However, the reorderings can be eliminated by using fences of appropriate strengths.