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Wideband high efficiency CMOS envelope amplifiers for 4G LTE handset envelope tracking RF power amplifiers


Fourth generation cellular networks offer performance similar to cable modems while allowing wide mobility. Although the use of orthogonal frequency division multiplexing in fourth generation increases its spectral efficiency but it also increases the peak-to-average power ratio of the transmitted signal. If a conventional power amplifier is used to transmit a high peak-to-average power ratio signal, then to meet the stringent linearity requirements, it will be operating 6 to 10 dB back-off from the maximum output power. This is the region where power amplifier has lower efficiency. To overcome the low efficiency problem, the envelope tracking power amplifier architecture has been proposed in the literature due to its feature of high efficiency over a wide power range. The overall efficiency of the envelope tracking system is the product of the power amplifier efficiency and the envelope amplifier efficiency, which provides the dynamically varying power supply voltage. This dissertation focuses on developing high efficiency envelope amplifiers for wideband applications. First, a CMOS envelope amplifier is developed which cuts the quiescent power dissipation by half over the conventional designs and also employs more accurate current sensing. In order to further improve its efficiency, a dynamic supply is provided on the linear amplifier, which improves the overall efficiency by 6% in measurements. Secondly, modeling of power amplifier operating under envelope shaping is described, in order to accurately predict the efficiency of the envelope amplifier. Also, the stability of the envelope amplifier is analyzed under nonlinear resistive load operation. The overall envelope tracking system achieves a record high efficiency of 43% for 20 MHz LTE signal using a GaAs power amplifier. Finally, another new architecture for CMOS envelope amplifier is developed for efficiency enhancement, using deadband controller. A linearized describing function analysis is done on the proposed architecture, to predict the frequency responses of each block, which matches pretty well with the simulations. The stacked implementation of linear and switching amplifiers allows 6V supply while using all 3.3V devices for them. This leads to integration of envelop amplifiers into submicron CMOS processes

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