UCLA

Carrier aggregation is an attractive approach to increasing the data rate in wireless communication.

The basic idea is to transmit and receive data on two (or more) different carriers, thus raising the data rate proportionally.

For example, Release 10 of the LTE mobile phone standard supports both intra-band and inter-band aggregation.

A receiver supporting several carriers may simply employ multiple signal paths and corresponding frequency synthesizers but at the cost of high power and extremely stringent isolation requirements among the local oscillators.

This research introduces an efficient carrier aggregation receiver architecture that employs one receive path and a single synthesizer.

The block-downconversion scalable receiver translates all of the channels to the baseband and utilizes a new digital image rejection technique to reconstruct the signals.

A receiver prototype realized in 45-nm CMOS technology along with an FPGA back end provides an image rejection ratio of at least 70~dB across the entire band

with a noise figure of 3.8~dB while consuming 15~mW, a factor of four less than the prior art.