Bridging Intermediate Representations to Achieve Hardware Design Language Translation
The hardware industry is currently beginning a trend towards a more productive hardware design flow. Many designers have been noticing for years a lack of efficiency when it comes to the design process. In response, research groups have been proposing tools and languages to improve productivity in this domain. Two such examples are LiveHD and Chisel. LiveHD is a framework that seeks to perform live synthesis and simulation, where live means that results for these tasks are achieved in seconds or minutes rather than hours. Chisel is a new hardware description language that focuses on using software abstractions to improve design reuse. The compilers for both works rely upon intermediate representations to model a design for their compiler. Having LiveHD and Chisel interact is currently impossible since the way in which they model hardware designs is different. This paper proposes an implementation of a translator that would bridge the gap between these two research efforts, allowing designers to reap the benefits of both and thus greatly improve their productivity during the design process.