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Synthesis of floating-point addition clusters on FPGAs using carry-save arithmetic

  • Author(s): Verma, A
  • Verma, AK
  • Parandeh-Afshar, H
  • Brisk, P
  • Ienne, P
  • et al.

Published Web Location

http://www1.cs.ucr.edu/faculty/philip/papers/conferences/fpl10/fpl10-fpadd.pdf
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Abstract

A new method to synthesize clusters of floating-point addition operations on FPGAs is presented. Similar to Altera's floating-point data path compiler, it performs normalization once, at the output of the cluster operation. All significands in the clustered operation are denormalized in parallel with respect to the largest exponent: a fixed-point compressor tree then sums the aligned significands, followed by normalization and rounding. Compared to Altera's floating-point datapath compiler, our method reduces the critical path delay by as much as 20%, and area by as much as 29% on Altera Stratix III FPGAs. © 2010 IEEE.

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