Skip to main content
eScholarship
Open Access Publications from the University of California

VHDL design representation in the VHDL synthesis system (VSS)

  • Author(s): Lis, Joseph S.
  • Gajski, Daniel D.
  • et al.
Abstract

This report describes the use of the VHSIC Hardware Description Language (VHDL) for synthesis in the VHDL Synthesis System (VSS). The corresponding internal representation of VHDL used in VSS will be described. We will illustrate the use of this representation to capture characteristics of four different design models (combinational, functional, register transfer, behavioral). Algorithms for compiling the VHDL description into the design representation will be discussed.

Main Content
Current View