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Interconnect Architecture Design for Emerging Integration Technologies

  • Author(s): Akgun, Itir;
  • Advisor(s): Xie, Yuan;
  • et al.
Abstract

As Moore’s Law slows down, new integration technologies emerge, such as 3D integration, silicon interposer-based 2.5D integration, and most recently, monolithic 3D integration. In addition to offering performance, bandwidth, and energy improvements due to shorter wirelength, emerging integration technologies pose new opportunities, challenges, and targets for interconnect design. Meanwhile, interconnect has become an increasingly crucial design target due to hardware, such as data-centric architectures, and software trends, with memory-bound and data-intensive applications, putting more pressure on the communication system which significantly impacts the system performance. Due to these reasons, our work focuses on designing interconnect architectures for emerging integration technologies, as interconnects and communication fabric increasingly take the center stage in architecture design in post-Moore era.

In this thesis, we introduce interconnect architecture design for various emerging integration technologies, following the trends in hardware and software domains. First, targeting emerging data-intensive workloads with high memory capacity and bandwidth requirements, we propose scalable, low latency, high bandwidth, and low energy network-on-chip architecture design for 3D-stacked memories, called memory networks, on silicon interposer. Second, we evaluate memory network architectures for high performance computing and propose techniques to further improve the memory network latency. Third, following the advances in silicon interposer-based 2.5D integration, we propose a network-on-chip chiplet for intellectual property reuse, as a communication chiplet for future chiplet-based heterogeneous SoCs. Finally, we provide design space exploration for interconnect architectures for monolithic 3D integration, to discover trade-offs and provide guidelines for network-on-chip design under unique interconnect characteristics.

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