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Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving


This paper introduces a technique based on seam carving to reduce the area of microuidic very large scale integration (mVLSI) chips. Seam carving repeatedly identifies small slices of the device that can be safely removed (carved) and patched without adversely affecting device functionality. Using non-linear seam carving we achieve an average improvement of 4:28x in area utilization and an average reduction in uid routing channel length of 53%.

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