UC Santa Cruz

OpenRAM is a configurable SRAM compiler which can be ported to many PDKs. As such, increasing possible configurations increases the number of such PDKs that can be used. We present a new option for OpenRAM memories to use an inverter delay chain for control signal timing instead of replica bitline timing. This option increases the number of PDKs to which OpenRAM can easily be ported. This thesis presents the design and implementation of this new control logic in OpenRAM. We also present a 1KB dual-port SRAM macro with this control logic taped-out for fabrication on a multi-project wafer.