Skip to main content
eScholarship
Open Access Publications from the University of California

RT level power analysis

  • Author(s): Zhu, Jianwen
  • Agrawal, Poonam
  • Gajski, Daniel D.
  • et al.
Abstract

Elevating power estimation to architectural and behavioral level is essential for design exploration beyond logic level. In contrast with purely statistical approach, an analytical model is presented to estimate the power consumption in datapath and controller for a given RT level design. Experimental result shows that order of magnitude speed-up over low level tools as well as satisfactory accuracy can be achieved. This work can also serve as the basis for behavioral level estimation tool.

Main Content
Current View