Allocation of functional units from realistic component libraries
Existing heuristics and algorithms used in High-Level Synthesis typically assume a direct mapping of hardware description language (HDL) operators to RT units. This assumption simplifies synthesis but requires complex technology mapping to fully utilize the functionality of complex RT components. In this paper, we present an algorithm employing a novel representation scheme to more efficiently map abstract HDL behavior to realistic RT-component behavior. It enables efficient usage of complex databook components, custom designed cells, previously synthesized RT modules, and RT module generators. This approach can be used to customize HLS tools to user-specific RT libraries.