UCLA

Time-Interleaving (TI) can relax the power-speed tradeoffs of analog-to-digital converter (ADC) and reduce their metastability error rate while it is not free. Track-and-hold (T&H) nonlinearity, noise and power are the main limitations of high-speed high-resolution and low-power ADCs. This dissertation introduces two efficient T&H design techniques to improve the performances of TI-ADCs without sophisticated calibrations. Two fabricated chips with 8b 2GS/s and 8b 8.8GS/s will be shown as the silicon verification of the proposed methods.

Two prototype ICs were designed during this work. First, a two-way time-interleaved pipelined ADC architecture was built upon a new concept of virtual-ground sampling, featuring merged front-end T/H, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the THD, bandwidth, and sample rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in a 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency.

Second, a complementary dual-loop-assisted track-and-hold buffer is introduced to achieve both high linearity and bandwidth with low power. The prototype ADC also employs a two-level 2�8 master-slave hierarchical interleaved architecture and achieved an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. It achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.