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Towards a Synthesizable Standard-Cell Radio

  • Author(s): Su, Richard Yu-Kuwan
  • Advisor(s): Pister, Kristofer
  • et al.
Abstract

Radios available today are designed to be high performance devices. These radios require careful design by experienced and skilled RF IC designers, more expensive RF processes, and large chip areas for RF passives. The resulting cost of these devices is at the dollar level without the off chip components, and the careful design required makes integration of these radios with other circuits (microprocessors, sensors, etc) an expensive proposition. We believe that radios that require limited design skills while still having good performance will enable widespread use of wireless technologies.

This motivation leads to the design of a fully integrated frequency shift keying (FSK) transceiver and phase-locked loops (PLLs) built with standard cells in a .18μm CMOS process without any off-chip components. Building a transceiver and PLLs with standard cells dictates that an inverter-based ring oscillator, rather than an LC oscillator, will be used for LO generation. Even though the frequency stability of a ring oscillator poses an obstacle in FSK modulation, this approach reduces the effort required when re-designing the receiver in a different process. Additionally, an inverter-based ring oscillator takes up much less area compared to an LC oscillator.

The receiver prototype built in a .18μm standard CMOS process occupies only 500μm x 350μm of area, has a sensitivity of -76dBm at 10kbps data rate, and consumes 6mW from a single 1.8V supply while operating in 915MHz ISM band.

The transmitter prototype built in a .18μm standard CMOS process includes a power amplifier and a fractional-N all-digital PLL. This fractional-N PLL uses an embedded time-to-digital converter (TDC) with multi-path to increase TDC resolution, and includes digital correction circuitry to resolve issues from clock skew. This PLL prototype occupies 500μm x 500μm of area, generates a 915MHz LO signal from a 10MHz reference, has phase noise of -90dBc/Hz at 1MHz offset and 2.62ps-rms jitter while consuming 4.2mA from a 1.8V supply. Even though this fractional-N all-digital PLL is built almost entirely with standard cells, the performance of this PLL is comparable to other state-of-the-art all-digital PLLs recently published in ISSCC. To illustrate the idea of portability, this transmitter in a .18μm standard CMOS process is ported to a 65nm CMOS process for completeness and this transmitter takes up 0.04mm2. In a fine-line process, a complete transceiver can occupy only 0.1mm2 of area or smaller.

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