UC San Diego

The thesis presents a W-band transmit-receive phased array and THz multiplier arrays in SiGe BiCMOS and CMOS technologies. First, a 4x4 transmit/receive SiGe BiCMOS phased array chip in an advanced SiGe technology (IBM8HP) at 90-100 GHz with vertical and horizontal polarization capabilities, 3-bit gain control (9 dB) and 4-bit phase control is presented. The 4x4 phased array fits into a 1.6x1.5 mm² grid, which is required at 94 GHz for wide scan-angle designs. The chip has simultaneous receive beam capabilities (V and H) and this is accomplished using dual -nested 16:1 Wilkinson combiners/divider with high isolation. The phase shifter is based on a vector- modulator with optimized design between circuit level and electromagnetic simulation and results in < 1 dB and < 7.5° rms gain and phase error, respectively, at 85-110 GHz. The behavior of the vector modulator phase distortion versus input power level is investigated and measured, and design guidelines are given for proper operation in a transmit chain. The V and H receive paths result in a gain of 22 dB and 25 dB, respectively, a noise figure of 9-9.5 dB (max. gain) and 11 dB (min. gain) measured without the T/R switch, and an input P1dB of -31 to -26 dBm over the gain control range. The measured output Psat is ~-5 dBm per channel, limited by the T/R switch loss. Measurements show ±0.6 dB and ±0.75 dB variation between the 4x4 array elements in the transmit mode (Psat) and receive mode, respectively, and < -40 dB coupling between the different channels on the chip. The chip consumes 1100 mA from a 2 V supply in both the transmit and receive modes. The design can be scaled to > 10,000 elements using polyimide redistribution layers on top of the chip and the application areas are in W-band radars for landing systems. Next, a CMOS amplifier-multiplier-antenna array capable of generating an EIRP of 3-4 dBm at 420 GHz is presented. The chip is built using a 45nm CMOS SOI (IBM12SOI) process and efficient on-chip antennas are used to extract the power out of the chip. The design is based on a 90-110 GHz distribution network with splitters and amplifiers, and a balanced quadrupler capable of delivering up > 100 [mu]W of power at 370-430 GHz. The amplifier-multiplier concept is proven on a 2x4 array, and can be also scaled to any NxM array using additional W- band splitters and amplifiers. Finally, a 2x2 amplifier- multiplier array with on-chip antennas at 163-180 GHz in 45 nm CMOS SOI technology is presented. The measured EIRP is > 2 dBm at 165-175 GHz with a peak value of 5 dBm at 170 GHz meeting the stringiest metal-density rules for antennas. The design is based on a 80-100 GHz distribution network with splitters and amplifiers, and a balanced doubler capable of delivering up > 0.5 mW of power at 170- 190 GHz