UC San Diego

The design of power distribution networks (PDNs) become increasingly complex and less margin, as the CMOS technology node continues to scale down into 10nm and below and the operating voltage of high-performance (HPm) logic keeps decreasing. As circuit density on a single chip doubles every two to three years, the current density is growing rapidly as well. As the application of machine learning and deep learning are emerging, more and more logic blocks, such as application-specic or heterogeneous integrations are needed on future application processors(APs). All of these requires a better design and analysis of methodology for PDNs.