UC Berkeley

Scaling of supply voltage V_dd has significantly slowed down since the 130 nm node. As a result, integrated circuit (IC) power consumption has been on the rapid rise. This presents a serious thermal management challenge and potential limiter of integration density as well as a rapidly growing portion of the world electricity demand. The problem lies in the 60 mV/dec swing limitation of any device involving charge flow over energy barrier (i.e., current state of art CMOS). This requires at least 60 mV to decrease the transistor current by 10X. The future low power or "green" energy efficient scenario would benefit from a device that is friendlier to V_dd scaling. A transistor where carriers tunnel through rather than flow over a barrier is not subject to this limitation. However, achieving sub 60 mV/dec at current ranges of interest and over many decades is not trivial when relying solely on transmission probability modulation (i.e., increase/decrease of tunnel barrier width). Instead, if the absence/presence of tunneling state overlap is exploited a sharp "off" to "on" transition is achievable. By engineering the transistor device structure such that this overlap (i.e., onset of tunneling) occurs in a region of high electric field results in steep sub 60 mV/dec response over many decades of current. One novel design utilizes heavily doped, ultra shallow N+/P+ junctions to achieve this "sudden tunneling overlap" effect. Another design involves use of ultra thin body silicon-on-insulator (5 nm) to achieve a similar effect. Simulation results show sub 500 mV V_dd is possible if suitable low-E_g material is introduced. Both designs have been fabricated in silicon and their measurement results are presented.