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Evaluating and optimizing the NERSC workload on knights landing

  • Author(s): Barnes, T
  • Cook, B
  • Deslippe, J
  • Doerfler, D
  • Friesen, B
  • He, Y
  • Kurth, T
  • Koskela, T
  • Lobet, M
  • Malas, T
  • Oliker, L
  • Ovsyannikov, A
  • Sarje, A
  • Vay, JL
  • Vincenti, H
  • Williams, S
  • Carrier, P
  • Wichmann, N
  • Wagner, M
  • Kent, P
  • Kerr, C
  • Dennis, J
  • et al.
Abstract

© 2016 IEEE. NERSC has partnered with 20 representative application teams to evaluate performance on the Xeon-Phi Knights Landing architecture and develop an application-optimization strategy for the greater NERSC workload on the recently installed Cori system. In this article, we present early case studies and summarized results from a subset of the 20 applications highlighting the impact of important architecture differences between the Xeon-Phi and traditional Xeon processors. We summarize the status of the applications and describe the greater optimization strategy that has formed.

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