High Frequency Multiphase Clock Generation Using Multipath Oscillators and Applications
Oscillators and frequency dividers are core building blocks in communications systems and processors used to provide proper synchronization for the flow of information. Different variations of the conventional ring oscillator that involve coupling of different oscillator-stages or different oscillators have been introduced to provide multiple-phases without penalizing the oscillation frequency. These variations, known as multipath ring oscillators, enable system
designers to relax the performance-power trade-off through parallelism. These oscillator structures, however, introduce additional degrees of freedom and expand the design space considerably which makes the process of designing them optimally a very difficult task.
This dissertation introduces an accurate analytical model and comprehensive analysis for multipath ring oscillators and frequency dividers. The results of the analysis are incorporated into an optimization algorithm that allows a designer to arrive at the desired optimal design at a very short time. The analysis explains the factors that affect the different performance metrics including the number of phases, oscillation frequency, phase noise, and oscillation-mode stability.
As an example application, a 48 Gb/s serializing transmitter is designed in 65nm CMOS technology using superharmonic injection-locked multipath ring oscillators to generate multiphase sampling clock signals for the various stages of the serializer. The ability to generate multiple clock phases at relatively high frequencies and low power cost allows significant power and area savings in the overall Transmitter.