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Efficient use of execution resources in multicore processor architectures

  • Author(s): DeVuyst, Matthew David
  • et al.
Abstract

As the microprocessor industry embraces multicore architectures, inherently parallel applications benefit directly as they easily transform into sets of homogeneous parallel threads. However, many applications do not t this model. These applications include legacy binaries compiled for a single thread of execution and inherently serial applications. The inability of these two kinds of applications to exploit multicore architectures has created a crisis for the microprocessor industry : customers have come to expect significant performance improvements in all of their application every processor generation, but recent multicore architectures have failed to meet those expectations for many applications. This dissertation explores ways in which these applications can run efficiently on multi core platforms. The performance of legacy binaries compiled for a single thread of execution can be improved through automatic parallelization. We introduce a new technique to automatically parallelize binaries as they are executing. The parallelization technique leverages the benefits of hardware transactional memory, a synchronization mechanism enabling optimistic concurrency. Our technique exploits this to parallelize code that a traditional parallelizing compiler would be unable to transform due to potential memory aliasing. Applications with fundamentally serial code can benefits from core customization. The more heterogeneous the cores are, the more likely that a given application will nd a core on which it runs efficiently. We investigate two forms of heterogeneity : that created on homogeneous hardware by unbalanced resource assignment, and heterogeneity created by hardware asymmetry. We first consider a homogeneous multicore system composed of multithreading cores. Often the best schedules on such a system are unbalanced. We propose a set of novel scheduling algorithms that consider unbalanced schedules to nd good application-to-core assignments. We consider objective functions of both performance and energy. We also explore how applications can benefit from diverse Isms by considering heterogeneous-ISA multicore systems. We propose a new technique to rapidly migrate a thread among cores of different Isms, allowing applications to take advantage of hardware heterogeneity for performance gain or energy savings

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