Skip to main content
eScholarship
Open Access Publications from the University of California

Minimizing Leakage Energy in FPGAs Using Intentional Post-Silicon Device Aging

  • Author(s): Wei, Sheng
  • Advisor(s): Potkonjak, Miodrag
  • et al.
Abstract

The presence of process variation (PV) in deep submicron technologies has become a major concern for energy optimization attempts on FPGAs. We develop a negative bias temperature instability (NBTI) aging-based post-silicon leakage energy optimization scheme that stresses the components that are not used or are off the critical paths to reduce the total leakage energy consumption. Furthermore, we obtain the input vectors for aging by formulating the aging objectives into a satisfiability (SAT) problem. We synthesize the low leakage energy designs on Xilinx Spartan6 FPGA and evaluate the leakage energy savings on a set of ITC99 and Opencores benchmarks.

Main Content
Current View