UCLA

Analog-to-digital converters (ADCs) are widely used in communication systems to interface analog and digital circuits. While the speed, power, and area of digital circuits directly benefit from the decreasing channel length of CMOS devices, analog circuits suffer from reduced headroom, lower intrinsic gain, and higher device mismatch. Consequently, it has been increasingly difficult to design high-speed and low-power pipelined ADCs using conventional op amps.

This work presents a pipelined ADC that employs novel "charge-steering" op amps to relax the trade-offs among speed, noise, and power consumption. Such op amps afford a fourfold increase in speed and a twofold reduction in noise for a given power consumption and voltage gain. Using a new clock gating technique, the ADC digitally calibrates the nonlinearity and gain error at full speed. A prototype realized in 65-nm CMOS technology achieves a resolution of 10 bits with a sampling rate of 800 MHz, a power consumption of 19 mW, an SNDR of 52.2 dB at Nyquist, and an FoM of 53 fJ/conversion-step. A new background calibration technique is also proposed to accommodate temperature and supply variations.