UC Berkeley

We present a SPICE-compatible neural-network- based compact model for advanced FETs. The model consists of an IV and QV network which have all terminal currents and charges and includes geometry dependence. The study of the activation functions is conducted to find the most efficient function for circuit simulations. The model is then implemented in Verilog- A with direct multiplication instead of loops to enhance the computational speed. We demonstrate and benchmark the neural network model performance in large circuit simulations with different network structures. It shows about 40 times speed improvement compared to the conventional compact model.