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Open Access Publications from the University of California

Communication synthesis in SpecC environment


In this report we outline the main problems of communication synthesis task in the context of SpecC Environment, with focus on issues related to System-On-a-Chip design and Intellectual Property interfacing. Given an architecture model, we present the models and transformations necessary for generating the final communication model. The major refinement steps are also discussed in various abstraction levels and for various types of communicating parties (hardware, software).

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