UC Berkeley

The past thirty years have seen rapid growth in products and technologies based on microelectromechanical systems (MEMS). However, one of the limiting factors in commercializing MEMS devices is packaging, which can be the most costly step in the manufacturing process. A MEMS package must protect the movable parts of the device while allowing it to interact with its surroundings. In addition, the miniaturization of sensors and actuators has made it possible to integrate MEMS fabrication with that of integrated circuit (IC) processing. Due to the varying requirements for different applications, a universal standard for packaging MEMS has been elusive. However, a growing trend has been the shift away from bonding a separate sealing substrate to the device substrate and toward thin film encapsulation. The latter method has the potential to reduce costs and materials usage while increasing device throughput and yield.

Two thin film encapsulation methods for creating large area packaged cavities on top of silicon substrates have been developed based on porous membrane structures. The first approach uses thin polysilicon as a permeable membrane. The polysilicon is deposited on top of a doped oxide using low pressure chemical vapor deposition (LPCVD) to a thickness less than 300 nm. High temperature annealing drives the dopant atoms from the oxide into the polysilicon film, creating gaps within the film through which hydrofluoric acid (HF) vapor penetrates and etches the buried oxide. In addition, a process of rapidly depositing oxides greater than 10 um thick without cracking due to residual stress has also been demonstrated. This is accomplished by using plasma enhanced chemical vapor deposition (PECVD) steps of 2.5 um thickness with interceding rapid thermal annealing (RTA). The permeable polysilicon membrane technology provides the foundation for wafer-level encapsulation of MEMS devices inside the cavities by depositing a thick structural layer either under vacuum or at arbitrary pressure environments.

The thin permeable polysilicon technique then evolves into a broader encapsulation method in which a semi-permeable film is constructed from carbon nanotubes (CNTs) and polysilicon. The dense forest of CNTs may be grown to a height from 10 um to hundreds of um as the structural foundation for the encapsulation layer. Conformally coating the CNTs with polysilicon by LPCVD generates natural pores within the thick membrane. HF vapor penetrates the semi-permeable film to selectively etch the bottom oxide layer, after which another polysilicon deposition seals the film, rendering it impermeable. The etching behavior has been characterized as a function of the CNT height and exposure time to HF vapor. The CNT/polysilicon thickness for a given vacuum-sealed cavity area has also been designed using finite element analysis (FEA). Furthermore, large sealing areas of more than 1x1 mm^2 have been successfully demonstrated. As such, this wafer-level encapsulation technology could find potential packaging applications of MEMS devices, including large area gyroscope structures.