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Off-detector electronics for a high-rate CSC detector

  • Author(s): Drego, N
  • Hawkins, D
  • Lankford, AJ
  • Li, Y
  • Medve, M
  • Pier, S
  • Schernau, M
  • Stoker, D
  • et al.
Abstract

Data acquisition (DAQ) electronics are described for a system of high-rate cathode strip chambers (CSC) in the forward region of A Toroidal LHC Apparatus (ATLAS) muon spectrometer. The system provides serial streams of control signals for switched capacitor array analog memories on the chambers and accepts a total of nearly 294 Gbit/s in serial raw data streams from 64 chambers in the design configuration. Processing of the data is done in two stages, leading to an output bandwidth of 2.56 Gbit/s. The architecture of the system is described, as are some important signal processing algorithms and hardware implementation details. Although designed for a specific application, the architecture is sufficiently general to be used in other contexts.

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