UCLA

Mixed signal circuit design often involves circuits that are time-varying or highly non-linear, which further results in systems that are difficult to characterize using established methodologies for linear time-invariant systems, thus designers are more than often forced to rely on intensive simulations for design. This dissertation explores design optimization for comparators, phase locked loops and ADC from three different perspectives.

First, a complete analysis for regenerative comparators is presented including noise, offsets and speed for the first time. Despite the fact that the comparators are time-varying and regenerative with infinite gain, simple equivalent circuits still accurately capture their operation. Design guideline are provided for different comparator architectures.

Second, a linearized analysis for phase locked loops using bang-bang phase detectors is presented. The high non-linear bang-bang phase detector is ascribed to an effective gain, whose physical meaning is interpreted in signal space. Closed form expressions for loop gain, output jitter and phase noise profile are obtained using transfer functions for the first time. Design guidelines are also provided.

Last, a 2.5GS/s 10bit 65mW ADC in 28nm CMOS FD-SOI without active amplifier and intensive digital calibration is presented. This highlights the potential of circuit design based on complete understandings. The fabricated ADC with considerably less complexity achieves comparable performance with state-of-arts. Different imperfections are quantitatively studied and compared with measurement.