UC Davis

The evolution of data processing at the Large Hadron Collider (LHC) requires advancements in thedesign and implementation of specialized hardware to manage large quantities of data generated by high-energy collisions of subatomic particles in experiments. The Application-Specific Integrated Circuit (ASIC) Design Group at Fermi Lab has developed an integrated chip that merges analog data acquisition systems with digital logic. This chip is designed to perform on-site classification of collision events, effectively distinguishing between low-energy, irrelevant particles and those important to high-energy physics investigations. This design integrates two versions of analog chips with a superpixel architecture, facilitating the direct application of neural network algorithms for data classification, thus significantly reducing the data bandwidth requirements by preprocessing data at the source. Using functional testing, design errors pertaining to undefined logic signals were addressed and corrected in the ASIC. To correct undefined logic signals in the ASIC chip, extensive simulations revealed issues with the testselect and encoderOut signals in the superPixel submodule, which initially included only row values for certain pixel coordinates. By converting these into a 2D signal array to encompass both rows and columns, the design was modified. Additional design updates included removing the scanCLK signal to simplify the clocking architecture and introducing a Resetnot signal across several modules to ensure the chip starts in a known, stable state. These corrections and enhancements have significantly improved the functionality and reliability of the ASIC.