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Radio Frequency Switch Design for 5G Communication and ESD Design on Advanced Technology

Creative Commons 'BY-NC' version 4.0 license

The evolving 5G requires high data rate, low latency and broad coverage. Many new technologies are developed to fulfill these requirements, including multi RAT, carrier aggregation, advanced slot-based framework, mm-wave bands, beamforming and MIMO. These technologies require high isolation and harmonic filtering, low insertion loss, high linearity and fast switching RF front-end switches. In this dissertation, a design example of 3.5GHz switch is depicted in chapter 2 and an ESD protected 28GHz travelling wave switch is shown in chapter 3, which achieves comparable performance with state-of-art design and is the first ESD protected travelling wave switch on SOI.

On the other hand, as IC process evolving, traditional CMOS technology cannot fulfill the high speed and low power requirements. Therefore, advanced processes, FinFET and FDSOI technology start to be widely used, following with rising of cost and increase design complexity. Therefore, ESD reliability becomes a major concern. In chapter 4, we proposed a high area efficiency Cell-by-Cell SCR, which can save die area and provide less degradation on RF, mm-wave and high-speed circuit performance due to its low parasitic associated with smaller area. To lower the trigger voltage, Cell-by-Cell DTSCR is proposed. Temperature effect of diode, SCR and DTSCR is illustrated, where the large performance variation across temperature of DTSCR rise a question mark for ESD designer.

Successful simulation before silicon is essential for first-silicon success and time-to-market, especially for high cost advanced technologies. So does for ESD protection. In chapter 5, 3D mixed-mode TCAD ESD simulation flow for FinFET devices is depicted. This flow covers mainstream ESD device type, including diode, ggMOS and SCR. Besides device level ESD simulation, chip level fast dynamic ESD protection simulation methodology using Verilog-A is developed. This methodology is verified with silicon and shows its capability to cover novel ESD devices and various ESD protection circuitry in chapter 6.

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