UC San Diego

With the CMOS process technology progress, transistor can achieve up to 260 GHz ft and fmax referenced to the top metal, it makes possible to develop lower cost circuits and blocks for THz high speed implementations such as active imagine system, short distance chip to chip communication systems and large scale high speed ultra low power switch networks. The dissertation shows an 8x1 phased array transmitter working at 370-410 GHz with peak EIRP of 8.5 dBm, a QPSK modulated 20 Gbit/s transceiver front end (including modulator, voltage control oscillator, power splitter, doubler, mixer and wide-band baseband amplifier.) at 155 GHz and two cross connected high peed ultra low power switch matrices (an 8x8 matrix up to 25 Gbit/s matrix and a 16x16 matrix built using four 8x8 matrix). All circuits and blocks are built using the Global Foundries 45 nm CMOS SOI (silicon on isotropic) process.