UCLA

The charge trap transistor (CTT) is a nonvolatile device used as an analogue neuron for neuromorphic computing. The device used in this thesis is a 22FDX GlobalFoundries device, made with an interfacial layer of silicon oxide and 3.3nm of hafnium oxide. This device operates by applying large gate voltage pulses, a process known as programming (PRG) which traps electrons in the hafnium oxide layer. To reverse this, negative gate voltage pulses are applied in a process known as erase (ERS). This thesis focuses on random telegraph noise (RTN), a type of noise that occurs due to the trapping and detrapping of electrons in this layer and is considered the largest limitation of bit precision in the CTT. Analysis is performed on the various parameters theorized to affect RTN and as a result, overall CTT stability. Initial experiments were performed using Taguchi’s Method, which indicated a correlation between the number of RTN events in a given period and the degree of programming. This experiment also indicated a correlation between the number of RTN events in a given period and the number of PRG/ERS cycles. After this initial series of experiments were performed, where these individual parameters were studied in further detail. Furthermore, other parameters analyzed in further detail including the magnitude of an ERS event, the duration of measurement, and measurement conditions.