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DPLL and Energy Harvesting Circuit for Low-Power and Miniaturized System Applications

  • Author(s): Wong, Chien-Heng
  • Advisor(s): Chang, Mau-Chung Frank
  • et al.
Abstract

As fabrication technology improves, computation ability has increased accordingly and enables new applications such as biomedical and health monitoring system, internet of things (IoT) and home security surveillance. To satisfy stringent requirements such as limited supply, power and area for these new specs of emerging applications, critical circuit blocks must operate under low supply voltage and if possible generate power from ambient environments. Besides, these new applications can be further popularized if costly off-chip passive components which occupies large PCB footprint can be avoided.

This thesis firstly introduces fundamentals of phase locked loop (PLL) which provides clock to all analog and digital circuits in systems. Then a 0.75V 0.014mm2 2.6GHz digital bang-bang PLL with dynamic double-tail phase detector and supply-noise-tolerant gm-controlled DCO is proposed. At last, this thesis introduces a fully integrated CMOS dual source adaptive thermoelectric and RF energy harvesting circuit with 110mV startup voltage. Both circuits adopt no off-chip devices and can operate under low voltage or harvest energy from ambient environments. The prototype DBBPLL has been implemented in a mainstream 28nm CMOS process and consumes 2.9mW at the same time achieves low in-band phase noise of -105dBc/Hz. The energy harvester is implemented in 28nm CMOS, it achieves a self-startup voltage of 110mV without RF input and 85mV at -16dBm input. The boost converter power conversion efficiency (PCE) is 25% and the harvester overall PCE is 10%.

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