Skip to main content
eScholarship
Open Access Publications from the University of California

UC Irvine

UC Irvine Electronic Theses and Dissertations bannerUC Irvine

Analysis and Design of Multi-Port Oscillators for mm-Wave Imaging Systems

Abstract

Frequency synthesizers are critical building blocks of many communication systems, including mm-wave imaging. The performance specication of frequency synthesizers, such as phase noise, quadrature phase accuracy, and frequency tuning, directly impacts the over-

all performance. In many practical applications the frequency synthesizer is realized as a phase-locked loop (PLL), which is a control system whose output follows the input reference signal's phase. The core block in a PLL is the voltage-controlled oscillator (VCO) whose frequency is adjustable by an input voltage. The resonator used in a VCO is generally realized as an LC tank, which can be replaced by a multi-port passive network that may lead to superior performance.

In this dissertation, a systematic method to analyze and design multi-port quadrature VCOs (QVCOs) is introduced and compared with conventional QVCOs. The method is based on multi-port oscillator theory that provides necessary and sufficient conditions for oscillation start-up, as well as finding an expression for the frequency of oscillation. Moreover, trade-offs between quadrature phase accuracy and power consumption are derived. The phase noise performance of such oscillators is studied and a technique to minimize it is proposed. As a demonstration a low phase-noise 40 GHz QVCO is designed and optimized based on this analysis and fabricated using a 65 nm CMOS process.

In the second part of this dissertation, a 55 - 67 GHz integer-N PLL is designed using a multi-mode VCO. The oscillation modes of the VCO are varied by modulating the coupling factor of a pair of coupled inductors using CMOS switches. The oscillation modes correspond to different frequency ranges, which enable wide frequency tuning with minimum impact on the other performance specfications. The PLL also includes an eight-stage of frequency

divider that is carefully designed to cover the wide frequency range of the VCO output. The PLL is fabricated using 65 nm CMOS technology.

In the final chapter, the design of an oscillator based on degenerate band edge (DBE) is presented. The DBE occurs at certain innite periodic structures that can be used in VCOs to reduce their sensitivity to the load. Multiple double-ladder networks with lumped and distributed elements to produce the DBE are studied. Moreover, active components that can be used in such oscillators including cross-coupled differential pair and tunnel diode are investigated. A design of a VCO based on a DBE structure and cross-coupled pair with transient-time simulation results is reported.

Main Content
For improved accessibility of PDF content, download the file to your device.
Current View