UC San Diego

The emerging 5G and mm-wave high data rate wireless communication applications have exacerbated the challenges of the PA design, especially for the commercial Si-based ICs. The complex wideband OFDM signals in these applications, with high PAPR, demand stringent PA requirements of linearity, and efficiency at both peak and backoff power levels. This dissertation addresses the design challenges for sub-6GHz and 28GHz CMOS and SiGe integrated PAs, by introducing novel techniques and presenting them with proper mathematical framework and modeling, alongside the hardware implementations that achieve record results.

Active load modulation, employed in Doherty and Chireix outphasing architectures, is one of the well-known techniques to improve the backoff efficiency of PAs. In theory, outphasing offers a better efficiency profile than Doherty, but it was traditionally believed that it works well only with voltage-mode PAs. However, recently it has been shown that for outphasing with current-mode PAs, if the input drive power reduced at backoff, good results can be achieved. In this dissertation a detailed mathematical analysis for current-mode outphasing is presented, and then the implemented 5.5GHz 45nm CMOS-SOI dual-input outphasing PA is discussed that achieves record average PAE of 30.9% while generating a 40MHz 64-QAM OFDM modulated signal with 7.9dB PAPR and 14dBm average output power.

At 28GHz band, the loss due to the integrated passive elements is one of the bottlenecks to achieve high efficiency. To address this issue a novel Chiriex combiner based on a “triaxial balun” is presented. An equivalent circuit model of the balun is introduced for the first time to make the analysis and design more straight forward. The implemented chip in 130nm SiGe BiCMOS process shows balun loss of only 0.5dB at 28GHz, and the dual-input outphasing PA achieves a record average PAE of 25.3% for an 8.1dB PAPR, 80MHz 64-QAM OFDM signal with average output power of 14.3dBm.

In phased array systems, it is not practical to employ individual digital predistortion (DPD) for each PA unit, and they must be inherently linear. A novel architecture named Single Input Linear Chireix (SILC) PA is introduced that not only has a high backoff efficiency but also has a linear response achieved by correcting the transistor related distortions using the systematic AM-AM and AM-PM variations. The implemented PA in 130nm SiGe process demonstrates 19dBm saturated output power with 34.4% peak PAE and 6-dB backoff PAE of >23% at 27.5GHz. The modulated signal performance using a 100MHz 64-QAM OFDM signal shows average output power of 11.9dBm with PAE >20%, EVM <5%, and ACLR<-33dBc without using predistortion.

For 28GHz applications that require small footprint, the 2-stack CMOS PAs can offer enough output power with high peak efficiency. In order to improve the linearity, it is desirable to design for a “sweet spot” in the 3rd order intermodulation (IM3) at a critical power, where the distortion is significantly decreased. By adding a large resistor with a proper value at the gate of the transistor, the power dependent leakage current is used to create a dynamic bias that results in a slight amount of gain expansion that counters the gain compression due to the saturation of the PA. Experimental result using a 2-stack 28GHz PA implemented with 45nm CMOS-SOI shows peak output power of 19dBm and 43% PAE, and can attain high linearity without predistortion. Two-tone measurements show the formation of sweet spots at which IM3 decreases on order of 5-10dB at output power levels of order of 5dB backed off from P1dB.