Logical Reasoning Techniques for Physical Layout in Deep Nanometer Technologies
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Logical Reasoning Techniques for Physical Layout in Deep Nanometer Technologies


As VLSI technologies are continuously evolving sub-10nm, design of the routable and manufacturable layout for integrated circuits (ICs) has been more challenging. To maintain power-performance-area-cost (PPAC) gains from many scaling barriers, IC design demands orchestrated innovations across the entire stages of the design-to-silicon infrastructure. For this design-technology co-optimization (DTCO) in each physical design stage, the holistic exploration is essential across all the design considerations due to the limited resources, high density, and complex conditional design rules. However, many conventional ways focus on divide-and-conquer-style sub-problems and/or heuristic approaches because of the huge search space of the problem, resulting in limited optimality. In this dissertation, we propose several constraint-based exact solving, i.e., constraint satisfaction problem (CSP), frameworks in various physical design questions related to standard cell placement and routing such as detailed routing, standard cell synthesis, and engineering change order (ECO). Our outcomes have the enhanced optimality compared to conventional approaches due to the concurrent manner between design considerations without any sequential/separate procedures. We utilize/select the appropriate logical reasoning technique, such as Integer Linear Programming (ILP), Boolean satisfiability (SAT), and Satisfiability Modulo Theories (SMT), depending on the problem characteristics. In detailed routing, routability (including pin-accessibility) between standard cells becomes a critical bottleneck due to the limited number of routing tracks, higher pin density, and complex design rules. To reduce turnaround time, we suggest a fast routability analysis framework to analyze routing feasibility by using SAT solving technology. Routability analysis framework produces design rule-correct routability assessment within only 0.02% of ILP runtime on average. Also, we propose a precise routability diagnosis framework to diagnose explicit reasons for design-rule violations (DRVs) in the form of human-interpretable explanations, while specifying conflicting design rules with a physical location. To maximize PPAC gains in DTCO of standard cell synthesis, the automation of standard cell layout is essential for smooth technology transition. Since many conventional approaches lack the optimality of the cell layout due to the sequential/heuristic manner, we propose a SMT-based automated standard cell synthesis framework, which simultaneously solves place-androute, through a novel dynamic pin allocation scheme without deploying any sequential/separate operations. After tackling the scalability by developing various search-space reduction techniques, our framework successfully generates a whole set of 7nm standard cell library. On top of complete cell libraries, we propose standard cell scaling framework which enables the parametric study of standard cell layout with respect to the scaled cell architectures. In particular, we strictly ensure the pin-accessibility of the cell layout, which is intrinsically restricted by limited track number, through our novel Boolean constraints, while maintaining the scaling advantages.

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