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An Improved Quadrature Direct Digital Frequency Synthesizer in an FPGA


The architecture and design of a high-speed quadrature direct digital frequency synthesizer (DDFS) is presented. The architecture is based on a novel multiplier-based angle-rotation algorithm that does not distort the magnitude of the sine and cosine outputs. This algorithm maps well into the DSP slices present in modern FPGAs. The design has a 32-bit frequency control word, 16-bit outputs, and a tuning resolution of 0.23 Hz at 1 GHz. Implemented in a Xilinx Virtex-7 FPGA, the design dissipates 54.9 mW of power, a performance previously attainable only in ASIC designs.

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