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New Low Power Techniques for High-Speed Wireline Receivers

  • Author(s): Atharav, No Name Given
  • Advisor(s): Razavi, Behzad
  • et al.
Abstract

With the rapidly increasing Internet traffic and storage volume, the aggregate I/O bandwidth requirements in wireline systems have been climbing at a rate of approximately 2-3 times every two years. Thus, the power consumption of wireline transceivers has become increasingly more critical as higher data rates and a larger number of lanes per chip are sought. This issue is further intensified by the trade-offs between the channel loss and the power dissipation, especially in the receive path.

While PAM4 signaling is attractive for lossier channels, it has mostly dictated receiver designs incorporating analog-to-digital converters (ADCs) with high power numbers. Non-return-to-zero (NRZ) receiver, on the other hand, can be realized in the analog domain, potentially consuming less power, but they must deal with a greater channel loss.

This research introduces a 56-Gb/s NRZ receiver that draws 50 mW while exhibiting bit error rate (BER) of less than BER 10^(-12) for a channel loss of 25 dB at 28 GHz and 13.5 dB at 14 GHz. Such a receiver can compete with PAM4 counterparts and/or serve as part of 112-Gb/s systems that must also support 56-Gb/s NRZ reception. This work demonstrates a threefold improvement in the power efficiency.

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