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Advanced Electrical Characterization of Semiconductor Nanowires

  • Author(s): Khanal, Devesh Raj
  • Advisor(s): Wu, Junqiao
  • et al.
Abstract

Over the past decade, semiconductor nanowires have emerged as a potential candidate for the continued miniaturization of microelectronics. However, there exist major problems in characterizing their basic electronic properties, which result from the difficulty of using conventional semiconductor characterization techniques such as the Hall effect on individual nanowires due to their small size and aspect ratio. As a result, alternative methods of quantifying their basic semiconducting properties, including carrier concentration and mobility are required. To date, the most common alternative to the Hall effect experiment is the field-effect transistor (FET) measurement, where the nanowire is assembled into a field-effect device and gated current-voltage curves are recorded.

Extracting information about the carrier concentration and mobility from FET measurements, however, requires a precise knowledge of the electrostatics of the nanowire, which are usually neglected in favor of analytical approximations. In this work,

a series of experiments and theoretical studies are presented, which are shown to both improve the accuracy of extracted values of carrier concentration and mobility as well as allow for the quantification of additional electronic properties such as the Fermi-level pinning position and the relative magnitudes of individual carrier scattering mechanisms.

In chapter 2, finite element modeling of the electrostatics of nanowire-gate devices is used to evaluate the validity of assumptions used in common analytical capacitance formulas. It is shown that assumptions about the nanowire-gate geometry, the semiconducting nature of the wire, and length of the nanowire device lead to significant misestimations of the nanowire-gate capacitance, which can result in equally significant misestimations of carrier mobility and concentration.

A method for quantitatively extracting Fermi level pinning information, using a combination of FET measurements and finite element electrostatics modeling, is presented in Chapter 3 using InN nanowires as an example. The results indicate that the Fermi-level at the non-polar sidewalls of the nanowires is pinned to between 0.6 - 0.8 eV below the conduction band minimum, in good agreement with InN thin films. In Chapter 4, universal mobility analysis is used to determine the relative magnitude of individual scattering mechanisms on carrier mobility using only FET measurements and thorough calculations of the nanowire-gate electrostatics. The techniques of extracting Fermi level pinning position and free carrier scattering mechanisms in Chapter 3 and 4 can be applied to single nanowires, which has yet to be reported elsewhere in the literature. Finally, Chapter 5 includes a theoretical study of the doping limitations of ultra-small diameter nanowires where quantum confinement appreciably perturbs the density of states.

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