UC Berkeley

The discrepancy between perceived spectrum shortage and the actual availability by measurements motivates the use of cognitive radio concepts. In this approach the radio locates and then transmits in unused or lightly used bands. If a wideband digital approach (on the order of GHz) to channel selection is taken to provide the necessary radio flexibility, there is a stringent dynamic range and speed requirement in the analog to digital conversion process. This arises from the large interfering signals which are effectively in-band since they are not removed by analog pre-filters. Given this extremely challenging wideband dynamic range goal, a fundamentally different mixed signal architecture has been pursued which is based on time domain signal cancellation. The objective of this thesis is therefore to analyze and implement critical aspects of this approach, with particular focus on the power requirements and silicon area.

This approach explores the use of a mixed analog with digital assistance architecture which uses multiple low to medium resolution ADCs with digital adaptive filters. The effective dynamic range of the front-end is enhanced by cancelling the unwanted interference in the time domain.

Interference cancellation performance is improved using oversampling and a digital dual adaptive signal processing technique that provides a low mean squared error for cancellation together with a large processing gain. The system could achieve at least 11 bit equivalent dynamic range for the desired weak signals using two 5-bit ADC's and a 7-bit DAC. In general, the Effective Bits from Dynamic Range Reduction (EBDR) for the system is equal to, or more than N+M bits, where N and M are resolutions of the two ADC's used.

The key components of the system are high speed medium resolution ADC's and they have been implemented to demonstrate the path to a low power small area solution. An asynchronous 1GS/s ADC with a peak SNDR of 31.5dB, ENOB 5.0 bits, is achieved by time interleaving two ADC's based on the binary equivalent successive approximation (SA) algorithm using a series capacitive ladder with input capacitance of 84fF. A simple extension of the SA algorithm essentially removes the ENOB degradation due to metastability from the comparator. The ADC's are fabricated in 65nm CMOS with an active area of 0.11mm², with a total power consumption of 6.7mW.

It is believed that the time domain approach for wideband, high dynamic range applications which has been explored in this thesis is a step towards the goal of a future radio system, in which the A/D conversion process is directly after the front-end low noise amplifiers.