Low-power research has flourished recently, in an attempt to address packaging and cooling concerns of current microprocessor designs, as well as battery life for mobile computers. In this paper, we propose and evaluate a high performance, energy efficient front-end architecture. We outline a low-power instruction cache configuration, and examine the benefit of decoupling the tag component of our cache from the data component. This decoupling enables a sophisticated cache replacement algorithm and an accurate, but energy efficient, mechanism for speculative fetching. Cache blocks are initially verified by the tag component of the cache -- those that miss in the cache can be speculatively brought in from lower levels of the memory hierarchy. We introduce and analyze a number of auxiliary structures that enhance this design and maintain consistency between the time of verification and the actual cache block lookup. Our power efficient cache configuration provides a 43% reduction in energy dissipation over a comparable prefetching scheme for the benchmarks we examine, while attaining slightly better performance (measured in instructions per nanosecond).

Pre-2018 CSE ID: CS2000-0657

The reorder buffer and register file of a modern superscalar processor are both critical components of the processor pipeline that can have a large impact on processor performance. Larger reorder buffers and register files provide larger windows of speculation to the processor and allow greater levels of instruction-level parallelism. However, the access time to these critical path structures can grow quite large when these structures increase in size, especially considering the number of ports required on such structures. In this paper, we propose two architectures that are better able to scale to future technology sizes. First we examine a pipelined register file architecture that reduces the cost of bypassing. This architecture features a small operand file that is used to store register operands for instructions waiting in reservation stations. This operand file is also updated by the writeback stage of the process pipeline to provide register bypassing and can allow instructions to share stored register operands, helping to further hide the latency of the pipelined register file access. Second, we examine an architecture that decouples the reorder buffer and register file from the critical path of the processor, replacing them with a smaller, speculative register file and an operand file. The reorder buffer and larger register file are moved off the critical path of the processor and are used to still provide precise exceptions and a means to recover register state in the event of branch mispeculation. The speculative register file and operand file provide the low-latency, scalable performance to enable the execution core to better meet the demands of future cycle times. This technique also completely removes the need to perform conventional register renaming from the processor and the need to perform register map checkpointing.

Pre-2018 CSE ID: CS2001-0689