Flash memory manufacturers are increasing storage density by leveraging multi-bit per cell NAND flash technology in the latest process nodes. Error rates and endurance can be significantly altered in each generation, and the manufacturers provide conservative guidelines for these metrics. Deeper understanding of the physical characteristics of flash devices can be used to develop a usage model which improves lifetime and reliability.

We developed a System on Chip (SoC) platform for flash memory testing, including a hardware memory controller and software for pattern generation and data processing. We have used the platform to characterize properties of a Triple Level Cell (TLC) flash memory device from a single vendor, and found behaviors have significantly changed from previous generations. Among these novel findings, manufacturers have built compensation mechanisms for some worst-case behaviors, such as inter-cell interference (ICI), but other effects become inherently more significant in the latest technologies.

With information about how certain behaviors affect reliability in both the short-term and toward the end of the product lifetime, this work provides speculation on the goals for coding schemes which target error mitigation.