NAND flash-based solid-state drives (SSDs) are becoming a staple in consumer electronics and high-performance computing. Limited resources and a lack of flexible prototyping platforms constrain NAND flash researchers to use software simulation of the chips, where simulation parameters are based on conservative values from datasheets, leading to missed research opportunities. A tool to explore low-level NAND flash behavior and performance would give researchers an easy way to validate and guide new research ideas and designs. We present the Ming II platform which gives researchers complete control over flash chips. It includes a custom board that connects to a platform FPGA system and provides an automated interface for acquiring fine-grain power, latency, and bit error measurements of flash operations. The Ming II software stack includes an open-source userspace library, Linux driver, and development environment that make it easy to develop new software that targets flash. Possible applications include measuring flash characteristics (latency, power, bit-error ratios, lifetime, etc.), verifying encryption/decryption and sanitization protocols, prototyping new flash translation layers (FTLs), and identifying performance and power tradeoffs.

Pre-2018 CSE ID: CS2012-0978

Systems that provide powerful transaction mechanisms often rely on write-ahead logging (WAL) implementations that were designed with slow, disk-based systems in mind. The emerging class of fast, byte-addressable, non-volatile memory (NVM) technologies (e.g., phase change memories, spin-torque MRAMs, and the memristor), however, present performance characteristics very different from both disks and flash-based SSDs. This paper addresses the problem of designing a WAL scheme optimized for these fast NVM-based storage systems. We examine the features that a system like ARIES, a WAL algorithm popular for databases, must provide and separate them from the implementation decisions ARIES makes to optimize for disk-based systems. We design a new NVM-optimized WAL scheme (called MARS) in tandem with a novel SSD multi-part atomic write primitive that combine to provide the same features as ARIES does without any of the disk-centric limitations. The new atomic write primitive makes the log's contents visible to the application, allowing for a simpler and faster implementation. MARS provides atomicity, durability, and high performance by leveraging the enormous internal bandwidth and high degree of parallelism that advanced SSDs will provide. We have implemented MARS and the novel visible atomic write primitive in a next-generation SSD. This paper demonstrates the overhead of the primitive is minimal compared to normal writes, and our hardware provides large speedups for transactional updates to hash tables, b-trees, and large graphs. MARS outperforms ARIES by up to 3.7x

Pre-2018 CSE ID: CS2012-0981