The modern world is run by semiconductor-based electronic systems. Due to continuous improvements in semiconductor device fabrication, there is a clear trend in the market towards the development of electronic devices and components that not only deliver enhanced computing power, but are also more compact. Thermal management has emerged as the primary challenge in this scenario where heat flux dissipation of electronic chips is increasing exponentially, but conventional cooling solutions such as conduction and convection are no longer feasible. To keep device junction temperatures within the safe operating limit, there is an urgent requirement for ultra-high-conductivity thermal substrates that not only absorb and transport large heat fluxes, but can also provide localized cooling to thermal hotspots.
This dissertation describes the design, modeling, and fabrication of a phase change-based, planar, ultra-thin, passive thermal transport system that is inspired by the concept of loop heat pipes and capillary pumped loops. Fabricated on silicon and Pyrex wafers using microfabrication techniques, the micro-columnated loop heat pipe (μCLHP) can be integrated directly with densely packed or multiply-stacked electronic substrates, to provide localized high-heat-flux thermal management. The μCLHP employs a dual-scale coherent porous silicon(CPS)-based micro-columnated wicking structure, where the primary CPS wick provides large capillary forces for fluid transport, while a secondary surface-wick maximizes the rate of thin-film evaporation. To overcome the wick thickness limitation encountered in conventional loop heat pipes, strategies based on MEMS surface micromachining techniques were developed to reduce parasitic heat flow from the evaporator to the compensation chamber of the device. Finite element analysis was used to confirm this reduction in a planar evaporator design, thus enabling the generation of a large motive temperature head for continuous device operation. To predict the overall heat carrying capacity of the μCLHP in the capillary pumping limit, an analytical model was developed to account for a steady state pressure balance in the device flow loop. Based on this model, a design optimization study, employing monotonicity analysis and numerical optimization techniques, was undertaken. It was found that an optimized μCLHP device can absorb heat fluxes as large as 1293 W/cm2 when water is used as a working fluid. A finite volume method-based numerical model was also developed to compute the rates of thin-film evaporation from the patterned surface of the secondary wick. The numerical results indicated that, by properly optimizing the dual-scale wick topology, allowable evaporative heat fluxes can be made commensurate with the heat flux performance predicted by the capillary pumping limit.
The latter part of the dissertation deals with the fabrication, packaging, and experimental testing of several in-plane-wicking micro loop heat pipe (μLHP) prototypes. These devices were fabricated on silicon and Pyrex substrates and closely resemble the μCLHP design philosophy, with the exception that the CPS wick is substituted with an easier to fabricate in-plane wick. A novel thermal-flux method was developed for the degassing and fluid charging of the μLHP prototypes. Experiments were conducted to study the process of evaporation and dynamics of the liquid and vapor phases in the device flow loop. Using these results, the overall device and individual component topologies critical to the operation of the two-phase flow loop were identified. A continuous two-phase device flow loop was demonstrated for applied evaporator heat fluxes as high as 41 W/cm2. The performance of these devices, currently found to be limited by the motive temperature head requirement, can be significantly improved by implementing the parasitic heat flow-reduction strategies developed in this work. The 3-D thin-film evaporation model, when integrated into the overall device modeling framework, will enable a design optimization of the micro-columnated wick for further device performance enhancements.
