ABSTRACT OF THE DISSERTATION A Time Amplifier Assisted FDC and DTC Linearization for Digital Fractional-N PLLs by Eslam Mohamed Sayed Ali Helal Doctor of Philosophy in Electrical Engineering (Electronic Circuits and Systems) University of California San Diego, 2021 Professor Ian A. Galton, Chair

Phase-locked loops (PLLs) are critical components in modern electronics communication systems, where they are used to synthesize local oscillator signals for modulation and demodulation in wireless transceivers. They are also used to clock digital-to-analog converters (DACs), analog-to-digital converters (ADCs), and digital processors. Most PLLs incorporate either analog filters and voltage-controlled oscillators (VCOs) or digital filters and digitally-controlled oscillators (DCOs). The former are called analog PLLs and the latter are called digital PLLs. To date, analog PLLs have the best phase error performance, but digital PLLs have the lowest circuit area and are more compatible with highly-scaled CMOS integrated circuit (IC) technology. Thus, improving the performance of digital PLLs has been the subject of intensive research for many years. The first chapter of this dissertation presents time-difference amplifier (TA) and its application to a digital fractional-N phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma (ΔΣ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL’s phase noise from DMRO noise. The paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed ΔΣ FDC digital gain calibration technique. The second chapter of this dissertation presents an entirely digital background calibration technique that adaptively measures and cancels error resulting from DTC component mismatches that would otherwise degrade the phase noise of digital PLLs with DTC-based quantization noise cancellation. This technique indirectly addresses the well-known DTC nonlinearity problem because it facilitates the use of inherently-linear DTCs comprised of cascades of 1-bit DTC stages. Such DTCs tend to introduce excessive error from component mismatches, which has heretofore hindered their application to low-jitter PLLs. Published digital predistortion techniques provide an alternate means of mitigating DTC nonlinearity, but their convergence rates are at least an order of magnitude slower than that of the presented technique. It also presents a rigorous mathematical analysis that precisely quantifies the calibration technique’s settling performance and provides conditions under which it is unconditionally stable.