The design of RF integrated circuits continues to challenge engineers and researchers, demanding new circuit topologies and transceiver architectures. New ideas often require new analysis techniques as well, so that the designer can insightfully quantify the underlying principles.

This research addresses three problems in RF circuits: (1) analysis of phase noise in phase/frequency detectors (PFDs), an essential component in RF synthesizers; (2) analysis of the relation between the phase noise of delay lines and ring oscillators; and (3) design of a new low-power RF CMOS receiver for IEEE 802.11a. The first analysis derives equations for the phase noise and shows that

an octave increase in the input frequency raises the phase noise by 6 dB if flicker noise is dominant and by 3 dB if white noise is dominant. The second analysis reveals a simple shaping function and also dispels the commonly-accepted premise that symmetric rise and fall times in a ring oscillator suppress the upconversion of

flicker noise. The third part deals with the design of a low-power 5-GHz receiver. While advances in the art have considerably reduced the power consumption of RF oscillators, frequency dividers, and analog-to-digital converters, the main receiver chain in 5-GHz systems draws a disproportionately high power, about 46 mW. It is therefore desirable to develop low-power RX front ends and baseband filters for WiFi applications. This work introduces a complete 5-GHz CMOS receiver that meets the 11a sensitivity, blocking, and filtering requirements while consuming 11.6 mW. This fourfold reduction in power is achieved through the use of a transformer as a low-noise amplifier, passive mixers, and non-invasive baseband filtering. A new analysis of passive current-driven mixers sheds light on their properties.