Electrostatic discharge (ESD) in integrated circuits (ICs) occurs due to charge transferbetween two components in close proximity with voltage imbalance. As a result of an ESD event, a high transient current (up to few tens of Amps) and large voltage (up to several tens of kV) can develop between the two components. This fast ( 150 ns) transient phenomenon can cause serious damage or degrade the performance of affected ICs. ESD results in about 35% of IC eld returns and is the cause of several billion dollars loss to the semiconductor industry per year. Even though most modern ICs have on-chip ESD protection circuitry embedded, static charge accumulation during transport and handling may exceed the limits of ESD protection and cause damage to the ICs. Advanced packaging schemes existing today are not amenable to rework if one or more dielets are ESD compromised. An on-chip ESD sensor would help in identifying and preventing the assembly of ESD compromised dielets in any advanced packaging schemes. In this dissertation, two approaches for on-chip ESD detection that can be employed on any die are presented: variable dielectric width capacitor, and vertical MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric eld and facilitate easy breakdown of the thin dielectric between the metal plates. The vertical MOSCAP array consists of a capacitor array connected in series. Both approaches were designed, simulated, fabricated, and experimentally characterized on GlobalFoundries 22 nm fully depleted silicon-on-insulator (FDSOI) technology. The designed vertical MOSCAP arrays were able to detect ESD events 6V while the variable dielectric width capacitor-based sensor is able to detect ESD voltages 40V . A Bayesian method was formulated for the estimation of ESD voltage using the sensors and experimentally validated. Mathematical formulation for sensitivity and confidence in ESD voltage estimation was developed which matches the results of Monte-Carlo simulations.

Finally, a novel high-power delivery network for the Silicon interconnect fabric (Si-IF), aheterogeneous wafer-scale integration platform, is also proposed. The system is capable of 42 kW output power delivery to dielets when supplied with a 50-kW input power. Power delivery network (PDN) modelling and simulations have been carried out to determine impedance spectrum and I2R losses. A 100 W experimental prototype was designed and evaluated to check the feasibility of the proposed architecture.