This research work aims at eliminating the off-chip RF SAW filters from frequency division duplexed (FDD) receivers. In the first approach, a monolithic passive RF filter was constructed using on-chip capacitors and bondwire inductors. The bondwire characteristics were studied in details and the effect of mutual inductive coupling between the bondwires on the filter performance was analyzed. Based on that, a bondwire configuration was proposed to improve the frequency response of the filter. The filter was implemented in 0.18 um CMOS process for WCDMA applications. In the second approach, the downconverting mixer linearity performance was improved. It was observed that BSIM3 CMOS model fails to predict the transistor linearity behavior perfectly at zero drain- source bias voltage. It was analytically shown using Volterra series analysis that the incorrect simulation of passive mixer linearity is a consequence of this anomaly. Using Volterra series analysis, the second-order, third- order and cross-modulation linearity of a passive mixer was studied and analytical expressions were obtained to reflect their dependence upon the mixer source and load impedances. Based on this, it was formulated that the mixer linearity can be improved by selectively filtering the downconverted transmitted signal at the mixer output. A novel filtering mechanism was proposed that comprised of another downconverting mixer in cascade with a trans- impedance amplifier. This approach was used to implement a CDMA-2000 receiver for PCS band (1.96 GHz) in 0.18 um CMOS process. The proposed technique improved the triple beat and IIP2 by 6.5 dB.