The fifth-generation (5G) wireless communication standard is being developed to supply faster

wireless data transfer to ever-growing number of cellular network subscribers, and millimeter-wave phasedarray

transceivers have been proven to be perfect candidates for 5G infrastructure. This dissertation focuses

on the design and implementation of phased-arrays at 28 GHz and 60 GHz using 45-nm CMOS SOI and

0.18-μm SiGe BiCMOS technologies, respectively. A common-leg transmit/receive phased-array front-end

module is implemented for high-efficiency and high-linearity 5G applications. The design flow is discussed

and the error-vector magnitude (EVM) measurements are demonstrated with 8 Gbps data-rate. Reusing

some of the sub-blocks of this design, a 28 GHz two-element passive bidirectional phased-array core-chip

is designed and flip-chip packaged. The details of this design is presented in the appendix. The 60 GHz

dual-polarized dual-beam wafer-scale phased-array transceiver addresses the challenges of building a

phased-array that is larger than the standard maximum reticle size (22x22 mm2) for increased coverage.

The design strategies are discussed as well as the system and communication link analysis. This work

shows the construction of infinite-element phased-arrays on a low-cost printed circuit board (PCB) using

only bondwires to form a functional wafer-scale array.