The performance of integrated circuits (IC) is becoming less predictable as technology scales to the sub-90-num regime. Disparate sources of variations stem from the manufacturing process and ultimately translate to a parametric yield loss. To improve parametric yield, efficient algorithms are required to accurately predict the performance of a circuit at the design stage. However, given the high complexity of design and the presence of a large number of correlated parameters that exhibit significant variations, traditional Monte Carlo (MC) method becomes inefficient as a large number of sampling points are required for an accurate statistical description of the circuit response.
To mitigate this problem, a novel methodology for statistical performance analysis is proposed by representing statistical processes in a deterministic way to determine the key characteristics of statistical distributions. The proposed methodology has been successfully applied to statistical full-chip leakage analysis and capacitance extraction. For statistical full-chip leakage analysis, a general framework has been provided to derive the full-chip leakage currents or powers as closed form functions of process variation parameters. To the best knowledge of the author, this is the first full-chip statistical leakage analysis algorithm considering all types of spatial correlations with only linear time complexity O(N). Furthermore, it is extendable to incremental analysis for even more promising computing speed for larger problem sizes. For statistical capacitance extraction, a 3D statistical capacitance extraction method called StatCap is proposed, in which orthogonal polynomials are used to represent the statistical processes and the analytic second-order orthogonal polynomials are derived from the capacitance integrated equations to give more accurate results without loss of efficiency compared to the linear models. Experimental results show that StatCap is two orders of magnitude faster than the recently proposed statistical approach and many orders of magnitude faster than the MC.
To improve parametric yield, not only efficient algorithms are required to accurately predict the performance of a circuit, but also efficient techniques are highly desirable for chip design. Toward this direction, a novel voltage binning technique is proposed in the last part of the dissertation. The proposed method makes it possible to predict maximum bin numbers required under the uniform binning scheme, and model the optimal binning scheme as a set-cover problem. To achieve the same yield as the uniform approach, the proposed method can significantly save the number of bins and only takes very small CPU time cost.
