The operation of the voltage-mode and current-mode sense amplifiers (VSA and CSA) is explained in detail. Analytical expressions for offset arising from random FET mismatch are derived. The mechanism of two offset reduction method for VSA is explained. The supply-dependent offset for CSA is shown. The offset combined with signal attenuation define a figure-of-merit. The current-mode sense amplifier is shown to be superior at VDD < 0.6 ~ 0.7V.

Frequency-division duplexing (FDD) radios are widely used in wireless communication standards and multi-radio coexistence. It requires that the duplexer prevent both TX signal and noise from entering the receiver front-end, while operating under full TX power. It also requires the receiver front-end circuits to be highly linear when the TX leakage channel is adjacent to the receive channel.This work describes the design of a dual-band electrical balance duplexer (EBD). The electrical balance duplexer supports dual-band TX-RX isolation for FDD operation at 5-7GHz. A network in the EBD can balance the antenna impedance (ZANT) in the TX channel and RX channel independently. The EBD provides >40dB isolation in an 80MHz channel bandwidth in the TX band (5-6GHz), for any ZANT(fTX) with VSWR≤2, and independently in the RX band (6-7GHz) when QANT≤4.3. The EBD is designed for ≤4dB RX IL and ≤3.8dB TX IL. Second, the properties of finite-Q LCR networks are derived. Simple results and derivations provide performance limits and design guidelines for the on-chip filter (two-port) and impedance synthesizer (one-port). General properties are given for the design of multi-band on-chip N-port LCR networks. Third, second-order baseband filter circuits for mixer-first receivers are designed for adjacent channel blocker tolerance. The design guidelines are given in simple expressions. The independent poles control by circuit elements is achieved. The prototype measurements verify the design. It can tolerate the maximum TX leakage from the dual-band EBD without gain compression and noise degradation. Finally, the mixer switch nonlinearity is analyzed. Expressions for IIP3 and B1dB are given, showing the impact of supply voltage, FET size, clock waveform, operating frequency and baseband load. The analysis matches the simulation very well. The dual-band EBD and the mixer-first receiver with second-order baseband filters are fabricated in 65nm RF-SOI CMOS technology. They support the FDD operation for Wi-Fi 6/6E application between 5-7GHz.